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commit 791fe5ecf909d573bcbf353b677b9404f9da0ed4
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Author: Mark Wielaard <mark@klomp.org>
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Date: Mon May 27 22:19:27 2019 +0200
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Expose rdrand and f16c through cpuid also if the host only has avx.
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The amd64 CPUID dirtyhelpers are mostly static since they emulate some
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existing CPU "family". The avx2 ("i7-4910MQ") CPUID variant however
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can "dynamicly" enable rdrand and/or f16c if the host supports them.
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Do the same for the avx_and_cx16 ("i5-2300") CPUID variant.
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https://bugs.kde.org/show_bug.cgi?id=408009
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diff --git a/VEX/priv/guest_amd64_defs.h b/VEX/priv/guest_amd64_defs.h
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index 4f34b41..a5de527 100644
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--- a/VEX/priv/guest_amd64_defs.h
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+++ b/VEX/priv/guest_amd64_defs.h
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@@ -165,7 +165,9 @@ extern void amd64g_dirtyhelper_storeF80le ( Addr/*addr*/, ULong/*data*/ );
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extern void amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st );
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extern void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st );
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extern void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st );
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-extern void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st );
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+extern void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st,
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+ ULong hasF16C,
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+ ULong hasRDRAND );
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extern void amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st,
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ULong hasF16C, ULong hasRDRAND );
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diff --git a/VEX/priv/guest_amd64_helpers.c b/VEX/priv/guest_amd64_helpers.c
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index e4cf7e2..182bae0 100644
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--- a/VEX/priv/guest_amd64_helpers.c
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+++ b/VEX/priv/guest_amd64_helpers.c
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@@ -3141,8 +3141,11 @@ void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st )
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address sizes : 36 bits physical, 48 bits virtual
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power management:
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*/
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-void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st )
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+void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st,
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+ ULong hasF16C, ULong hasRDRAND )
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{
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+ vassert((hasF16C >> 1) == 0ULL);
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+ vassert((hasRDRAND >> 1) == 0ULL);
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# define SET_ABCD(_a,_b,_c,_d) \
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do { st->guest_RAX = (ULong)(_a); \
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st->guest_RBX = (ULong)(_b); \
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@@ -3157,9 +3160,14 @@ void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st )
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case 0x00000000:
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SET_ABCD(0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69);
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break;
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- case 0x00000001:
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- SET_ABCD(0x000206a7, 0x00100800, 0x1f9ae3bf, 0xbfebfbff);
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+ case 0x00000001: {
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+ // As a baseline, advertise neither F16C (ecx:29) nor RDRAND (ecx:30),
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+ // but patch in support for them as directed by the caller.
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+ UInt ecx_extra
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+ = (hasF16C ? (1U << 29) : 0) | (hasRDRAND ? (1U << 30) : 0);
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+ SET_ABCD(0x000206a7, 0x00100800, (0x1f9ae3bf | ecx_extra), 0xbfebfbff);
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break;
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+ }
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case 0x00000002:
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SET_ABCD(0x76035a01, 0x00f0b0ff, 0x00000000, 0x00ca0000);
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break;
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diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
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index 56e992c..96dee38 100644
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--- a/VEX/priv/guest_amd64_toIR.c
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+++ b/VEX/priv/guest_amd64_toIR.c
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@@ -22007,7 +22007,8 @@ Long dis_ESC_0F (
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vassert(fName); vassert(fAddr);
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IRExpr** args = NULL;
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- if (fAddr == &amd64g_dirtyhelper_CPUID_avx2) {
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+ if (fAddr == &amd64g_dirtyhelper_CPUID_avx2
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+ || fAddr == &amd64g_dirtyhelper_CPUID_avx_and_cx16) {
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Bool hasF16C = (archinfo->hwcaps & VEX_HWCAPS_AMD64_F16C) != 0;
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Bool hasRDRAND = (archinfo->hwcaps & VEX_HWCAPS_AMD64_RDRAND) != 0;
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args = mkIRExprVec_3(IRExpr_GSPTR(),
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diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
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index 3536e57..56a28d1 100644
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--- a/coregrind/m_machine.c
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+++ b/coregrind/m_machine.c
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@@ -1076,10 +1076,10 @@ Bool VG_(machine_get_hwcaps)( void )
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have_avx2 = (ebx & (1<<5)) != 0; /* True => have AVX2 */
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}
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- /* Sanity check for RDRAND and F16C. These don't actually *need* AVX2, but
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- it's convenient to restrict them to the AVX2 case since the simulated
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- CPUID we'll offer them on has AVX2 as a base. */
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- if (!have_avx2) {
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+ /* Sanity check for RDRAND and F16C. These don't actually *need* AVX, but
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+ it's convenient to restrict them to the AVX case since the simulated
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+ CPUID we'll offer them on has AVX as a base. */
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+ if (!have_avx) {
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have_f16c = False;
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have_rdrand = False;
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}
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