Blame SOURCES/glibc-rh696472.patch

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commit 3d29045b5e8329d97693eda8d98f1d1e60b99c8f
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Author: H.J. Lu <hongjiu.lu@intel.com>
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Date:   Fri Jun 3 07:01:25 2011 -0400
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    Assume Intel Core i3/i5/i7 processor if AVX is available
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2011-06-02  H.J. Lu  <hongjiu.lu@intel.com>
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	* sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
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	Assume Intel Core i3/i5/i7 processor if AVX is available.
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diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c
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index 34ec2df..809d105 100644
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--- a/sysdeps/x86_64/multiarch/init-arch.c
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+++ b/sysdeps/x86_64/multiarch/init-arch.c
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@@ -74,6 +74,7 @@ __init_cpu_features (void)
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 	}
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       else if (family == 0x06)
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 	{
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+	  ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
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 	  model += extended_model;
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 	  switch (model)
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 	    {
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@@ -83,6 +84,12 @@ __init_cpu_features (void)
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 	      __cpu_features.feature[index_Slow_BSF] |= bit_Slow_BSF;
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 	      break;
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+	    default:
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+	      /* Unknown family 0x06 processors.  Assuming this is one
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+	         of Core i3/i5/i7 processors if AVX is available.  */
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+	      if ((ecx & bit_AVX) == 0)
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+		break;
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+
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 	    case 0x1a:
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 	    case 0x1e:
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 	    case 0x1f: