arrfab / rpms / glibc

Forked from rpms/glibc 4 years ago
Clone

Blame SOURCES/glibc-rh1240351-12.patch

147e83
    Backport of
147e83
    commit ce6615c9c686acd34672a9f4eba9bcf5553496f6
147e83
    Author: Adhemerval Zanella <azanella@linux.vnet.ibm.com>
147e83
    Date:   Sun Jan 11 19:33:17 2015 -0600
147e83
    
147e83
        powerpc: Fix POWER7/PPC64 performance regression on LE
147e83
    
147e83
        This patch fixes a performance regression on the POWER7/PPC64 memcmp
147e83
        porting for Little Endian.  The LE code uses 'ldbrx' instruction to read
147e83
        the memory on byte reversed form, however ISA 2.06 just provide the indexed
147e83
        form which uses a register value as additional index, instead of a fixed value
147e83
        enconded in the instruction.
147e83
    
147e83
        And the port strategy for LE uses r0 index value and update the address
147e83
        value on each compare loop interation.  For large compare size values,
147e83
        it adds 8 more instructions plus some more depending of trailing
147e83
        size.  This patch fixes it by adding pre-calculate indexes to remove the
147e83
        address update on loops and tailing sizes.
147e83
    
147e83
        For large sizes it shows a considerable gain, with double performance
147e83
        pairing with BE.
147e83
    
147e83
        ChangeLog:
147e83
    	2015-01-13  Adhemerval Zanella  <azanella@linux.vnet.ibm.com>
147e83
    
147e83
    	* sysdeps/powerpc/powerpc64/power7/memcmp.S (memcmp): Fix performance
147e83
    	regression on LE.
147e83
147e83
diff --git a/sysdeps/powerpc/powerpc64/power7/memcmp.S b/sysdeps/powerpc/powerpc64/power7/memcmp.S
147e83
index 09bff69..98b9e54 100644
147e83
--- a/sysdeps/powerpc/powerpc64/power7/memcmp.S
147e83
+++ b/sysdeps/powerpc/powerpc64/power7/memcmp.S
147e83
@@ -26,18 +26,48 @@
147e83
 EALIGN (memcmp, 4, 0)
147e83
 	CALL_MCOUNT 3
147e83
 
147e83
-#define rRTN	r3
147e83
-#define rSTR1	r3	/* first string arg */
147e83
-#define rSTR2	r4	/* second string arg */
147e83
-#define rN	r5	/* max string length */
147e83
-#define rWORD1	r6	/* current word in s1 */
147e83
-#define rWORD2	r7	/* current word in s2 */
147e83
-#define rWORD3	r8	/* next word in s1 */
147e83
-#define rWORD4	r9	/* next word in s2 */
147e83
-#define rWORD5	r10	/* next word in s1 */
147e83
-#define rWORD6	r11	/* next word in s2 */
147e83
-#define rWORD7	r30	/* next word in s1 */
147e83
-#define rWORD8	r31	/* next word in s2 */
147e83
+#define rRTN		r3
147e83
+#define rSTR1		r3	/* first string arg */
147e83
+#define rSTR2		r4	/* second string arg */
147e83
+#define rN		r5	/* max string length */
147e83
+#define rWORD1		r6	/* current word in s1 */
147e83
+#define rWORD2		r7	/* current word in s2 */
147e83
+#define rWORD3		r8	/* next word in s1 */
147e83
+#define rWORD4		r9	/* next word in s2 */
147e83
+#define rWORD5		r10	/* next word in s1 */
147e83
+#define rWORD6		r11	/* next word in s2 */
147e83
+
147e83
+#define rOFF8		r20	/* 8 bytes offset.  */
147e83
+#define rOFF16  	r21	/* 16 bytes offset.  */
147e83
+#define rOFF24		r22	/* 24 bytes offset.  */
147e83
+#define rOFF32		r23	/* 24 bytes offset.  */
147e83
+#define rWORD6_SHIFT	r24	/* Left rotation temp for rWORD8.  */
147e83
+#define rWORD4_SHIFT	r25	/* Left rotation temp for rWORD6.  */
147e83
+#define rWORD2_SHIFT	r26	/* Left rotation temp for rWORD4.  */
147e83
+#define rWORD8_SHIFT	r27	/* Left rotation temp for rWORD2.  */
147e83
+#define rSHR		r28	/* Unaligned shift right count.  */
147e83
+#define rSHL		r29	/* Unaligned shift left count.  */
147e83
+#define rWORD7		r30	/* next word in s1 */
147e83
+#define rWORD8		r31	/* next word in s2 */
147e83
+
147e83
+#define rWORD8SAVE	(-8)
147e83
+#define rWORD7SAVE	(-16)
147e83
+#define rOFF8SAVE	(-24)
147e83
+#define rOFF16SAVE	(-32)
147e83
+#define rOFF24SAVE	(-40)
147e83
+#define rOFF32SAVE	(-48)
147e83
+#define rSHRSAVE	(-56)
147e83
+#define rSHLSAVE	(-64)
147e83
+#define rWORD8SHIFTSAVE	(-72)
147e83
+#define rWORD2SHIFTSAVE	(-80)
147e83
+#define rWORD4SHIFTSAVE	(-88)
147e83
+#define rWORD6SHIFTSAVE	(-96)
147e83
+
147e83
+#ifdef __LITTLE_ENDIAN__
147e83
+# define LD	ldbrx
147e83
+#else
147e83
+# define LD	ldx
147e83
+#endif
147e83
 
147e83
 	xor	r0, rSTR2, rSTR1
147e83
 	cmpldi	cr6, rN, 0
147e83
@@ -51,10 +81,24 @@ EALIGN (memcmp, 4, 0)
147e83
 /* If less than 8 bytes or not aligned, use the unaligned
147e83
    byte loop.  */
147e83
 	blt	cr1, L(bytealigned)
147e83
-	std	rWORD8, -8(r1)
147e83
-	cfi_offset(rWORD8, -8)
147e83
-	std	rWORD7, -16(r1)
147e83
-	cfi_offset(rWORD7, -16)
147e83
+	std	rWORD8, rWORD8SAVE(r1)
147e83
+	cfi_offset(rWORD8, rWORD8SAVE)
147e83
+	std	rWORD7, rWORD7SAVE(r1)
147e83
+	cfi_offset(rWORD7, rWORD7SAVE)
147e83
+	std	rOFF8, rOFF8SAVE(r1)
147e83
+	cfi_offset(rWORD7, rOFF8SAVE)
147e83
+	std	rOFF16, rOFF16SAVE(r1)
147e83
+	cfi_offset(rWORD7, rOFF16SAVE)
147e83
+	std	rOFF24, rOFF24SAVE(r1)
147e83
+	cfi_offset(rWORD7, rOFF24SAVE)
147e83
+	std	rOFF32, rOFF32SAVE(r1)
147e83
+	cfi_offset(rWORD7, rOFF32SAVE)
147e83
+
147e83
+	li	rOFF8,8
147e83
+	li	rOFF16,16
147e83
+	li	rOFF24,24
147e83
+	li	rOFF32,32
147e83
+
147e83
 	bne	L(unaligned)
147e83
 /* At this point we know both strings have the same alignment and the
147e83
    compare length is at least 8 bytes.  r12 contains the low order
147e83
@@ -79,15 +123,8 @@ L(samealignment):
147e83
 	sldi	rWORD6, r12, 3
147e83
 	srdi	r0, rN, 5	/* Divide by 32 */
147e83
 	andi.	r12, rN, 24	/* Get the DW remainder */
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 0(rSTR1)
147e83
-	ld	rWORD2, 0(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, 0, rSTR1
147e83
+	LD	rWORD2, 0, rSTR2
147e83
 	cmpldi	cr1, r12, 16
147e83
 	cmpldi	cr7, rN, 32
147e83
 	clrldi	rN, rN, 61
147e83
@@ -104,15 +141,8 @@ L(dsP1):
147e83
 	cmpld	cr5, rWORD5, rWORD6
147e83
 	blt	cr7, L(dP1x)
147e83
 /* Do something useful in this cycle since we have to branch anyway.  */
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 8(rSTR1)
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF8, rSTR1
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	b	L(dP1e)
147e83
 /* Remainder is 16 */
147e83
@@ -123,15 +153,8 @@ L(dPs2):
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	blt	cr7, L(dP2x)
147e83
 /* Do something useful in this cycle since we have to branch anyway.  */
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD7, 8(rSTR1)
147e83
-	ld	rWORD8, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF8, rSTR1
147e83
+	LD	rWORD8, rOFF8, rSTR2
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	b	L(dP2e)
147e83
 /* Remainder is 24 */
147e83
@@ -173,72 +196,43 @@ L(dP1):
147e83
    change any on the early exit path.  The key here is the non-early
147e83
    exit path only cares about the condition code (cr5), not about which
147e83
    register pair was used.  */
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 0(rSTR1)
147e83
-	ld	rWORD6, 0(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, 0, rSTR1
147e83
+	LD	rWORD6, 0, rSTR2
147e83
 	cmpld	cr5, rWORD5, rWORD6
147e83
 	blt	cr7, L(dP1x)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 8(rSTR1)
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF8, rSTR1
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 L(dP1e):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 16(rSTR1)
147e83
-	ld	rWORD4, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF16, rSTR1
147e83
+	LD	rWORD4, rOFF16, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 24(rSTR1)
147e83
-	ld	rWORD6, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, rOFF24, rSTR1
147e83
+	LD	rWORD6, rOFF24, rSTR2
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	bne	cr5, L(dLcr5x)
147e83
 	bne	cr7, L(dLcr7x)
147e83
 
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ldu	rWORD7, 32(rSTR1)
147e83
-	ldu	rWORD8, 32(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF32, rSTR1
147e83
+	LD	rWORD8, rOFF32, rSTR2
147e83
+	addi	rSTR1, rSTR1, 32
147e83
+	addi	rSTR2, rSTR2, 32
147e83
 	bne	cr1, L(dLcr1)
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	bdnz	L(dLoop)
147e83
 	bne	cr6, L(dLcr6)
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 	.align	3
147e83
 L(dP1x):
147e83
 	sldi.	r12, rN, 3
147e83
 	bne	cr5, L(dLcr5x)
147e83
 	subfic	rN, r12, 64	/* Shift count is 64 - (rN * 8).  */
147e83
 	bne	L(d00)
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 0
147e83
 	blr
147e83
 
147e83
@@ -246,79 +240,41 @@ L(dP1x):
147e83
 	.align	4
147e83
 L(dP2):
147e83
 	mtctr	r0
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 0(rSTR1)
147e83
-	ld	rWORD6, 0(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, 0, rSTR1
147e83
+	LD	rWORD6, 0, rSTR2
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	blt	cr7, L(dP2x)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD7, 8(rSTR1)
147e83
-	ld	rWORD8, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF8, rSTR1
147e83
+	LD	rWORD8, rOFF8, rSTR2
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 L(dP2e):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 16(rSTR1)
147e83
-	ld	rWORD2, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF16, rSTR1
147e83
+	LD	rWORD2, rOFF16, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 24(rSTR1)
147e83
-	ld	rWORD4, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF24, rSTR1
147e83
+	LD	rWORD4, rOFF24, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
-#ifndef __LITTLE_ENDIAN__
147e83
 	addi	rSTR1, rSTR1, 8
147e83
 	addi	rSTR2, rSTR2, 8
147e83
-#endif
147e83
 	bne	cr6, L(dLcr6)
147e83
 	bne	cr5, L(dLcr5)
147e83
 	b	L(dLoop2)
147e83
-/* Again we are on a early exit path (16-23 byte compare), we want to
147e83
-   only use volatile registers and avoid restoring non-volatile
147e83
-   registers.  */
147e83
 	.align	4
147e83
 L(dP2x):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 8(rSTR1)
147e83
-	ld	rWORD4, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF8, rSTR1
147e83
+	LD	rWORD4, rOFF8, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 	sldi.	r12, rN, 3
147e83
 	bne	cr6, L(dLcr6x)
147e83
-#ifndef __LITTLE_ENDIAN__
147e83
 	addi	rSTR1, rSTR1, 8
147e83
 	addi	rSTR2, rSTR2, 8
147e83
-#endif
147e83
 	bne	cr1, L(dLcr1x)
147e83
 	subfic	rN, r12, 64	/* Shift count is 64 - (rN * 8).  */
147e83
 	bne	L(d00)
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 0
147e83
 	blr
147e83
 
147e83
@@ -326,52 +282,22 @@ L(dP2x):
147e83
 	.align	4
147e83
 L(dP3):
147e83
 	mtctr	r0
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 0(rSTR1)
147e83
-	ld	rWORD4, 0(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, 0, rSTR1
147e83
+	LD	rWORD4, 0, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 L(dP3e):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 8(rSTR1)
147e83
-	ld	rWORD6, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, rOFF8, rSTR1
147e83
+	LD	rWORD6, rOFF8, rSTR2
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	blt	cr7, L(dP3x)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD7, 16(rSTR1)
147e83
-	ld	rWORD8, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF16, rSTR1
147e83
+	LD	rWORD8, rOFF16, rSTR2
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 24(rSTR1)
147e83
-	ld	rWORD2, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF24, rSTR1
147e83
+	LD	rWORD2, rOFF24, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
-#ifndef __LITTLE_ENDIAN__
147e83
 	addi	rSTR1, rSTR1, 16
147e83
 	addi	rSTR2, rSTR2, 16
147e83
-#endif
147e83
 	bne	cr1, L(dLcr1)
147e83
 	bne	cr6, L(dLcr6)
147e83
 	b	L(dLoop1)
147e83
@@ -380,26 +306,21 @@ L(dP3e):
147e83
    registers.  */
147e83
 	.align	4
147e83
 L(dP3x):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 16(rSTR1)
147e83
-	ld	rWORD2, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF16, rSTR1
147e83
+	LD	rWORD2, rOFF16, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	sldi.	r12, rN, 3
147e83
 	bne	cr1, L(dLcr1x)
147e83
-#ifndef __LITTLE_ENDIAN__
147e83
 	addi	rSTR1, rSTR1, 16
147e83
 	addi	rSTR2, rSTR2, 16
147e83
-#endif
147e83
 	bne	cr6, L(dLcr6x)
147e83
 	subfic	rN, r12, 64	/* Shift count is 64 - (rN * 8).  */
147e83
 	bne	cr7, L(dLcr7x)
147e83
 	bne	L(d00)
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 0
147e83
 	blr
147e83
 
147e83
@@ -407,46 +328,20 @@ L(dP3x):
147e83
 	.align	4
147e83
 L(dP4):
147e83
 	mtctr	r0
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 0(rSTR1)
147e83
-	ld	rWORD2, 0(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, 0, rSTR1
147e83
+	LD	rWORD2, 0, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 L(dP4e):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 8(rSTR1)
147e83
-	ld	rWORD4, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF8, rSTR1
147e83
+	LD	rWORD4, rOFF8, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 16(rSTR1)
147e83
-	ld	rWORD6, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, rOFF16, rSTR1
147e83
+	LD	rWORD6, rOFF16, rSTR2
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ldu	rWORD7, 24(rSTR1)
147e83
-	ldu	rWORD8, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF24, rSTR1
147e83
+	LD	rWORD8, rOFF24, rSTR2
147e83
+	addi	rSTR1, rSTR1, 24
147e83
+	addi	rSTR2, rSTR2, 24
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	bne	cr7, L(dLcr7)
147e83
 	bne	cr1, L(dLcr1)
147e83
@@ -454,51 +349,25 @@ L(dP4e):
147e83
 /* This is the primary loop */
147e83
 	.align	4
147e83
 L(dLoop):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 8(rSTR1)
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF8, rSTR1
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 	bne	cr6, L(dLcr6)
147e83
 L(dLoop1):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 16(rSTR1)
147e83
-	ld	rWORD4, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF16, rSTR1
147e83
+	LD	rWORD4, rOFF16, rSTR2
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	bne	cr5, L(dLcr5)
147e83
 L(dLoop2):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 24(rSTR1)
147e83
-	ld	rWORD6, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, rOFF24, rSTR1
147e83
+	LD	rWORD6, rOFF24, rSTR2
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	bne	cr7, L(dLcr7)
147e83
 L(dLoop3):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ldu	rWORD7, 32(rSTR1)
147e83
-	ldu	rWORD8, 32(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF32, rSTR1
147e83
+	LD	rWORD8, rOFF32, rSTR2
147e83
+	addi	rSTR1, rSTR1, 32
147e83
+	addi	rSTR2, rSTR2, 32
147e83
 	bne	cr1, L(dLcr1)
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	bdnz	L(dLoop)
147e83
@@ -519,62 +388,75 @@ L(d14):
147e83
 	sldi.	r12, rN, 3
147e83
 	bne	cr5, L(dLcr5)
147e83
 L(d04):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 	subfic	rN, r12, 64	/* Shift count is 64 - (rN * 8).  */
147e83
-	beq	L(zeroLength)
147e83
+	beq	L(duzeroLength)
147e83
 /* At this point we have a remainder of 1 to 7 bytes to compare.  Since
147e83
    we are aligned it is safe to load the whole double word, and use
147e83
    shift right double to eliminate bits beyond the compare length.  */
147e83
 L(d00):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 8(rSTR1)
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF8, rSTR1
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	srd	rWORD1, rWORD1, rN
147e83
 	srd	rWORD2, rWORD2, rN
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	bne	cr7, L(dLcr7x)
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 0
147e83
 	blr
147e83
 
147e83
 	.align	4
147e83
 L(dLcr7):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 L(dLcr7x):
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 1
147e83
 	bgtlr	cr7
147e83
 	li	rRTN, -1
147e83
 	blr
147e83
 	.align	4
147e83
 L(dLcr1):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 L(dLcr1x):
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 1
147e83
 	bgtlr	cr1
147e83
 	li	rRTN, -1
147e83
 	blr
147e83
 	.align	4
147e83
 L(dLcr6):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 L(dLcr6x):
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 1
147e83
 	bgtlr	cr6
147e83
 	li	rRTN, -1
147e83
 	blr
147e83
 	.align	4
147e83
 L(dLcr5):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 L(dLcr5x):
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 1
147e83
 	bgtlr	cr5
147e83
 	li	rRTN, -1
147e83
@@ -583,10 +465,6 @@ L(dLcr5x):
147e83
 	.align	4
147e83
 L(bytealigned):
147e83
 	mtctr	rN
147e83
-#if 0
147e83
-/* Huh?  We've already branched on cr6!  */
147e83
-	beq	cr6, L(zeroLength)
147e83
-#endif
147e83
 
147e83
 /* We need to prime this loop.  This loop is swing modulo scheduled
147e83
    to avoid pipe delays.  The dependent instruction latencies (load to
147e83
@@ -685,6 +563,7 @@ L(b11):
147e83
 L(bx12):
147e83
 	sub	rRTN, rWORD1, rWORD2
147e83
 	blr
147e83
+
147e83
 	.align	4
147e83
 L(zeroLength):
147e83
 	li	rRTN, 0
147e83
@@ -705,42 +584,36 @@ L(zeroLength):
147e83
    we need to adjust the length (rN) and special case the loop
147e83
    versioning for the first DW. This ensures that the loop count is
147e83
    correct and the first DW (shifted) is in the expected resister pair.  */
147e83
-#define rSHL		r29	/* Unaligned shift left count.  */
147e83
-#define rSHR		r28	/* Unaligned shift right count.  */
147e83
-#define rWORD8_SHIFT	r27	/* Left rotation temp for rWORD2.  */
147e83
-#define rWORD2_SHIFT	r26	/* Left rotation temp for rWORD4.  */
147e83
-#define rWORD4_SHIFT	r25	/* Left rotation temp for rWORD6.  */
147e83
-#define rWORD6_SHIFT	r24	/* Left rotation temp for rWORD8.  */
147e83
 L(unaligned):
147e83
-	std	rSHL, -24(r1)
147e83
-	cfi_offset(rSHL, -24)
147e83
+	std	rSHL, rSHLSAVE(r1)
147e83
+	cfi_offset(rSHL, rSHLSAVE)
147e83
 	clrldi	rSHL, rSTR2, 61
147e83
 	beq	cr6, L(duzeroLength)
147e83
-	std	rSHR, -32(r1)
147e83
-	cfi_offset(rSHR, -32)
147e83
+	std	rSHR, rSHRSAVE(r1)
147e83
+	cfi_offset(rSHR, rSHRSAVE)
147e83
 	beq	cr5, L(DWunaligned)
147e83
-	std	rWORD8_SHIFT, -40(r1)
147e83
-	cfi_offset(rWORD8_SHIFT, -40)
147e83
+	std	rWORD8_SHIFT, rWORD8SHIFTSAVE(r1)
147e83
+	cfi_offset(rWORD8_SHIFT, rWORD8SHIFTSAVE)
147e83
 /* Adjust the logical start of rSTR2 to compensate for the extra bits
147e83
    in the 1st rSTR1 DW.  */
147e83
 	sub	rWORD8_SHIFT, rSTR2, r12
147e83
 /* But do not attempt to address the DW before that DW that contains
147e83
    the actual start of rSTR2.  */
147e83
 	clrrdi	rSTR2, rSTR2, 3
147e83
-	std	rWORD2_SHIFT, -48(r1)
147e83
-	cfi_offset(rWORD2_SHIFT, -48)
147e83
+	std	rWORD2_SHIFT, rWORD2SHIFTSAVE(r1)
147e83
+	cfi_offset(rWORD2_SHIFT, rWORD2SHIFTSAVE)
147e83
 /* Compute the left/right shift counts for the unaligned rSTR2,
147e83
    compensating for the logical (DW aligned) start of rSTR1.  */
147e83
 	clrldi	rSHL, rWORD8_SHIFT, 61
147e83
 	clrrdi	rSTR1, rSTR1, 3
147e83
-	std	rWORD4_SHIFT, -56(r1)
147e83
-	cfi_offset(rWORD4_SHIFT, -56)
147e83
+	std	rWORD4_SHIFT, rWORD4SHIFTSAVE(r1)
147e83
+	cfi_offset(rWORD4_SHIFT, rWORD4SHIFTSAVE)
147e83
 	sldi	rSHL, rSHL, 3
147e83
 	cmpld	cr5, rWORD8_SHIFT, rSTR2
147e83
 	add	rN, rN, r12
147e83
 	sldi	rWORD6, r12, 3
147e83
-	std	rWORD6_SHIFT, -64(r1)
147e83
-	cfi_offset(rWORD6_SHIFT, -64)
147e83
+	std	rWORD6_SHIFT, rWORD6SHIFTSAVE(r1)
147e83
+	cfi_offset(rWORD6_SHIFT, rWORD6SHIFTSAVE)
147e83
 	subfic	rSHR, rSHL, 64
147e83
 	srdi	r0, rN, 5	/* Divide by 32 */
147e83
 	andi.	r12, rN, 24	/* Get the DW remainder */
147e83
@@ -750,25 +623,13 @@ L(unaligned):
147e83
    this may cross a page boundary and cause a page fault.  */
147e83
 	li	rWORD8, 0
147e83
 	blt	cr5, L(dus0)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
+	LD	rWORD8, 0, rSTR2
147e83
 	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD8, 0(rSTR2)
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#endif
147e83
 	sld	rWORD8, rWORD8, rSHL
147e83
 
147e83
 L(dus0):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 0(rSTR1)
147e83
-	ld	rWORD2, 0(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, 0, rSTR1
147e83
+	LD	rWORD2, 0, rSTR2
147e83
 	cmpldi	cr1, r12, 16
147e83
 	cmpldi	cr7, rN, 32
147e83
 	srd	r12, rWORD2, rSHR
147e83
@@ -796,12 +657,7 @@ L(dusP1):
147e83
 	beq	L(duZeroReturn)
147e83
 	li	r0, 0
147e83
 	ble	cr7, L(dutrim)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	b	L(dutrim)
147e83
 /* Remainder is 16 */
147e83
@@ -832,27 +688,21 @@ L(duPs4):
147e83
    compare length is at least 8 bytes.  */
147e83
 	.align	4
147e83
 L(DWunaligned):
147e83
-	std	rWORD8_SHIFT, -40(r1)
147e83
-	cfi_offset(rWORD8_SHIFT, -40)
147e83
+	std	rWORD8_SHIFT, rWORD8SHIFTSAVE(r1)
147e83
+	cfi_offset(rWORD8_SHIFT, rWORD8SHIFTSAVE)
147e83
 	clrrdi	rSTR2, rSTR2, 3
147e83
-	std	rWORD2_SHIFT, -48(r1)
147e83
-	cfi_offset(rWORD2_SHIFT, -48)
147e83
+	std	rWORD2_SHIFT, rWORD2SHIFTSAVE(r1)
147e83
+	cfi_offset(rWORD2_SHIFT, rWORD2SHIFTSAVE)
147e83
 	srdi	r0, rN, 5	/* Divide by 32 */
147e83
-	std	rWORD4_SHIFT, -56(r1)
147e83
-	cfi_offset(rWORD4_SHIFT, -56)
147e83
+	std	rWORD4_SHIFT, rWORD4SHIFTSAVE(r1)
147e83
+	cfi_offset(rWORD4_SHIFT, rWORD4SHIFTSAVE)
147e83
 	andi.	r12, rN, 24	/* Get the DW remainder */
147e83
-	std	rWORD6_SHIFT, -64(r1)
147e83
-	cfi_offset(rWORD6_SHIFT, -64)
147e83
+	std	rWORD6_SHIFT, rWORD6SHIFTSAVE(r1)
147e83
+	cfi_offset(rWORD6_SHIFT, rWORD6SHIFTSAVE)
147e83
 	sldi	rSHL, rSHL, 3
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
+	LD	rWORD6, 0, rSTR2
147e83
+	LD	rWORD8, rOFF8, rSTR2
147e83
 	addi	rSTR2, rSTR2, 8
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD6, 0(rSTR2)
147e83
-	ldu	rWORD8, 8(rSTR2)
147e83
-#endif
147e83
 	cmpldi	cr1, r12, 16
147e83
 	cmpldi	cr7, rN, 32
147e83
 	clrldi	rN, rN, 61
147e83
@@ -867,52 +717,26 @@ L(DWunaligned):
147e83
 	.align	4
147e83
 L(duP1):
147e83
 	srd	r12, rWORD8, rSHR
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-#else
147e83
-	ld	rWORD7, 0(rSTR1)
147e83
-#endif
147e83
+	LD	rWORD7, 0, rSTR1
147e83
 	sld	rWORD8_SHIFT, rWORD8, rSHL
147e83
 	or	rWORD8, r12, rWORD6_SHIFT
147e83
 	blt	cr7, L(duP1x)
147e83
 L(duP1e):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 8(rSTR1)
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF8, rSTR1
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	sld	rWORD2_SHIFT, rWORD2, rSHL
147e83
 	or	rWORD2, r0, rWORD8_SHIFT
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 16(rSTR1)
147e83
-	ld	rWORD4, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF16, rSTR1
147e83
+	LD	rWORD4, rOFF16, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	srd	r12, rWORD4, rSHR
147e83
 	sld	rWORD4_SHIFT, rWORD4, rSHL
147e83
 	bne	cr5, L(duLcr5)
147e83
 	or	rWORD4, r12, rWORD2_SHIFT
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 24(rSTR1)
147e83
-	ld	rWORD6, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, rOFF24, rSTR1
147e83
+	LD	rWORD6, rOFF24, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 	srd	r0, rWORD6, rSHR
147e83
 	sld	rWORD6_SHIFT, rWORD6, rSHL
147e83
@@ -932,82 +756,47 @@ L(duP1x):
147e83
 	beq	L(duZeroReturn)
147e83
 	li	r0, 0
147e83
 	ble	cr7, L(dutrim)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	b	L(dutrim)
147e83
 /* Remainder is 16 */
147e83
 	.align	4
147e83
 L(duP2):
147e83
 	srd	r0, rWORD8, rSHR
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-#else
147e83
-	ld	rWORD5, 0(rSTR1)
147e83
-#endif
147e83
+	LD	rWORD5, 0, rSTR1
147e83
 	or	rWORD6, r0, rWORD6_SHIFT
147e83
 	sld	rWORD6_SHIFT, rWORD8, rSHL
147e83
 L(duP2e):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD7, 8(rSTR1)
147e83
-	ld	rWORD8, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF8, rSTR1
147e83
+	LD	rWORD8, rOFF8, rSTR2
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	srd	r12, rWORD8, rSHR
147e83
 	sld	rWORD8_SHIFT, rWORD8, rSHL
147e83
 	or	rWORD8, r12, rWORD6_SHIFT
147e83
 	blt	cr7, L(duP2x)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 16(rSTR1)
147e83
-	ld	rWORD2, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF16, rSTR1
147e83
+	LD	rWORD2, rOFF16, rSTR2
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	bne	cr6, L(duLcr6)
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	sld	rWORD2_SHIFT, rWORD2, rSHL
147e83
 	or	rWORD2, r0, rWORD8_SHIFT
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 24(rSTR1)
147e83
-	ld	rWORD4, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF24, rSTR1
147e83
+	LD	rWORD4, rOFF24, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	bne	cr5, L(duLcr5)
147e83
 	srd	r12, rWORD4, rSHR
147e83
 	sld	rWORD4_SHIFT, rWORD4, rSHL
147e83
 	or	rWORD4, r12, rWORD2_SHIFT
147e83
-#ifndef __LITTLE_ENDIAN__
147e83
 	addi	rSTR1, rSTR1, 8
147e83
 	addi	rSTR2, rSTR2, 8
147e83
-#endif
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 	b	L(duLoop2)
147e83
 	.align	4
147e83
 L(duP2x):
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
-#ifndef __LITTLE_ENDIAN__
147e83
 	addi	rSTR1, rSTR1, 8
147e83
 	addi	rSTR2, rSTR2, 8
147e83
-#endif
147e83
 	bne	cr6, L(duLcr6)
147e83
 	sldi.	rN, rN, 3
147e83
 	bne	cr5, L(duLcr5)
147e83
@@ -1015,12 +804,7 @@ L(duP2x):
147e83
 	beq	L(duZeroReturn)
147e83
 	li	r0, 0
147e83
 	ble	cr7, L(dutrim)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	b	L(dutrim)
147e83
 
147e83
@@ -1028,73 +812,39 @@ L(duP2x):
147e83
 	.align	4
147e83
 L(duP3):
147e83
 	srd	r12, rWORD8, rSHR
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-#else
147e83
-	ld	rWORD3, 0(rSTR1)
147e83
-#endif
147e83
+	LD	rWORD3, 0, rSTR1
147e83
 	sld	rWORD4_SHIFT, rWORD8, rSHL
147e83
 	or	rWORD4, r12, rWORD6_SHIFT
147e83
 L(duP3e):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 8(rSTR1)
147e83
-	ld	rWORD6, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, rOFF8, rSTR1
147e83
+	LD	rWORD6, rOFF8, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 	srd	r0, rWORD6, rSHR
147e83
 	sld	rWORD6_SHIFT, rWORD6, rSHL
147e83
 	or	rWORD6, r0, rWORD4_SHIFT
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD7, 16(rSTR1)
147e83
-	ld	rWORD8, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF16, rSTR1
147e83
+	LD	rWORD8, rOFF16, rSTR2
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	bne	cr1, L(duLcr1)
147e83
 	srd	r12, rWORD8, rSHR
147e83
 	sld	rWORD8_SHIFT, rWORD8, rSHL
147e83
 	or	rWORD8, r12, rWORD6_SHIFT
147e83
 	blt	cr7, L(duP3x)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 24(rSTR1)
147e83
-	ld	rWORD2, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF24, rSTR1
147e83
+	LD	rWORD2, rOFF24, rSTR2
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	bne	cr6, L(duLcr6)
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	sld	rWORD2_SHIFT, rWORD2, rSHL
147e83
 	or	rWORD2, r0, rWORD8_SHIFT
147e83
-#ifndef __LITTLE_ENDIAN__
147e83
 	addi	rSTR1, rSTR1, 16
147e83
 	addi	rSTR2, rSTR2, 16
147e83
-#endif
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	b	L(duLoop1)
147e83
 	.align	4
147e83
 L(duP3x):
147e83
-#ifndef __LITTLE_ENDIAN__
147e83
 	addi	rSTR1, rSTR1, 16
147e83
 	addi	rSTR2, rSTR2, 16
147e83
-#endif
147e83
-#if 0
147e83
-/* Huh?  We've already branched on cr1!  */
147e83
-	bne	cr1, L(duLcr1)
147e83
-#endif
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	bne	cr6, L(duLcr6)
147e83
 	sldi.	rN, rN, 3
147e83
@@ -1103,12 +853,7 @@ L(duP3x):
147e83
 	beq	L(duZeroReturn)
147e83
 	li	r0, 0
147e83
 	ble	cr7, L(dutrim)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	b	L(dutrim)
147e83
 
147e83
@@ -1117,51 +862,27 @@ L(duP3x):
147e83
 L(duP4):
147e83
 	mtctr	r0
147e83
 	srd	r0, rWORD8, rSHR
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-#else
147e83
-	ld	rWORD1, 0(rSTR1)
147e83
-#endif
147e83
+	LD	rWORD1, 0, rSTR1
147e83
 	sld	rWORD2_SHIFT, rWORD8, rSHL
147e83
 	or	rWORD2, r0, rWORD6_SHIFT
147e83
 L(duP4e):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 8(rSTR1)
147e83
-	ld	rWORD4, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF8, rSTR1
147e83
+	LD	rWORD4, rOFF8, rSTR2
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	srd	r12, rWORD4, rSHR
147e83
 	sld	rWORD4_SHIFT, rWORD4, rSHL
147e83
 	or	rWORD4, r12, rWORD2_SHIFT
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 16(rSTR1)
147e83
-	ld	rWORD6, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, rOFF16, rSTR1
147e83
+	LD	rWORD6, rOFF16, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 	bne	cr7, L(duLcr7)
147e83
 	srd	r0, rWORD6, rSHR
147e83
 	sld	rWORD6_SHIFT, rWORD6, rSHL
147e83
 	or	rWORD6, r0, rWORD4_SHIFT
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ldu	rWORD7, 24(rSTR1)
147e83
-	ldu	rWORD8, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF24, rSTR1
147e83
+	LD	rWORD8, rOFF24, rSTR2
147e83
+	addi	rSTR1, rSTR1, 24
147e83
+	addi	rSTR2, rSTR2, 24
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	bne	cr1, L(duLcr1)
147e83
 	srd	r12, rWORD8, rSHR
147e83
@@ -1172,60 +893,34 @@ L(duP4e):
147e83
 /* This is the primary loop */
147e83
 	.align	4
147e83
 L(duLoop):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD1, 8(rSTR1)
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF8, rSTR1
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 	bne	cr6, L(duLcr6)
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	sld	rWORD2_SHIFT, rWORD2, rSHL
147e83
 	or	rWORD2, r0, rWORD8_SHIFT
147e83
 L(duLoop1):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD3, 0, rSTR1
147e83
-	ldbrx	rWORD4, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD3, 16(rSTR1)
147e83
-	ld	rWORD4, 16(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD3, rOFF16, rSTR1
147e83
+	LD	rWORD4, rOFF16, rSTR2
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
 	bne	cr5, L(duLcr5)
147e83
 	srd	r12, rWORD4, rSHR
147e83
 	sld	rWORD4_SHIFT, rWORD4, rSHL
147e83
 	or	rWORD4, r12, rWORD2_SHIFT
147e83
 L(duLoop2):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD5, 0, rSTR1
147e83
-	ldbrx	rWORD6, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD5, 24(rSTR1)
147e83
-	ld	rWORD6, 24(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD5, rOFF24, rSTR1
147e83
+	LD	rWORD6, rOFF24, rSTR2
147e83
 	cmpld	cr5, rWORD7, rWORD8
147e83
 	bne	cr7, L(duLcr7)
147e83
 	srd	r0, rWORD6, rSHR
147e83
 	sld	rWORD6_SHIFT, rWORD6, rSHL
147e83
 	or	rWORD6, r0, rWORD4_SHIFT
147e83
 L(duLoop3):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD7, 0, rSTR1
147e83
-	ldbrx	rWORD8, 0, rSTR2
147e83
-	addi	rSTR1, rSTR1, 8
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ldu	rWORD7, 32(rSTR1)
147e83
-	ldu	rWORD8, 32(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD7, rOFF32, rSTR1
147e83
+	LD	rWORD8, rOFF32, rSTR2
147e83
+	addi	rSTR1, rSTR1, 32
147e83
+	addi	rSTR2, rSTR2, 32
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
 	bne	cr1, L(duLcr1)
147e83
 	srd	r12, rWORD8, rSHR
147e83
@@ -1234,10 +929,6 @@ L(duLoop3):
147e83
 	bdnz	L(duLoop)
147e83
 
147e83
 L(duL4):
147e83
-#if 0
147e83
-/* Huh?  We've already branched on cr1!  */
147e83
-	bne	cr1, L(duLcr1)
147e83
-#endif
147e83
 	cmpld	cr1, rWORD3, rWORD4
147e83
 	bne	cr6, L(duLcr6)
147e83
 	cmpld	cr6, rWORD5, rWORD6
147e83
@@ -1264,99 +955,102 @@ L(du14):
147e83
 	beq	L(duZeroReturn)
147e83
 	li	r0, 0
147e83
 	ble	cr7, L(dutrim)
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD2, 0, rSTR2
147e83
-	addi	rSTR2, rSTR2, 8
147e83
-#else
147e83
-	ld	rWORD2, 8(rSTR2)
147e83
-#endif
147e83
+	LD	rWORD2, rOFF8, rSTR2
147e83
 	srd	r0, rWORD2, rSHR
147e83
 	.align	4
147e83
 L(dutrim):
147e83
-#ifdef __LITTLE_ENDIAN__
147e83
-	ldbrx	rWORD1, 0, rSTR1
147e83
-#else
147e83
-	ld	rWORD1, 8(rSTR1)
147e83
-#endif
147e83
+	LD	rWORD1, rOFF8, rSTR1
147e83
 	ld	rWORD8, -8(r1)
147e83
 	subfic	rN, rN, 64	/* Shift count is 64 - (rN * 8).  */
147e83
 	or	rWORD2, r0, rWORD8_SHIFT
147e83
-	ld	rWORD7, -16(r1)
147e83
-	ld	rSHL, -24(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
+	ld	rSHL, rSHLSAVE(r1)
147e83
 	srd	rWORD1, rWORD1, rN
147e83
 	srd	rWORD2, rWORD2, rN
147e83
-	ld	rSHR, -32(r1)
147e83
-	ld	rWORD8_SHIFT, -40(r1)
147e83
+	ld	rSHR, rSHRSAVE(r1)
147e83
+	ld	rWORD8_SHIFT, rWORD8SHIFTSAVE(r1)
147e83
 	li	rRTN, 0
147e83
 	cmpld	cr7, rWORD1, rWORD2
147e83
-	ld	rWORD2_SHIFT, -48(r1)
147e83
-	ld	rWORD4_SHIFT, -56(r1)
147e83
+	ld	rWORD2_SHIFT, rWORD2SHIFTSAVE(r1)
147e83
+	ld	rWORD4_SHIFT, rWORD4SHIFTSAVE(r1)
147e83
 	beq	cr7, L(dureturn24)
147e83
 	li	rRTN, 1
147e83
-	ld	rWORD6_SHIFT, -64(r1)
147e83
+	ld	rWORD6_SHIFT, rWORD6SHIFTSAVE(r1)
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	bgtlr	cr7
147e83
 	li	rRTN, -1
147e83
 	blr
147e83
 	.align	4
147e83
 L(duLcr7):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 	li	rRTN, 1
147e83
 	bgt	cr7, L(dureturn29)
147e83
-	ld	rSHL, -24(r1)
147e83
-	ld	rSHR, -32(r1)
147e83
+	ld	rSHL, rSHLSAVE(r1)
147e83
+	ld	rSHR, rSHRSAVE(r1)
147e83
 	li	rRTN, -1
147e83
 	b	L(dureturn27)
147e83
 	.align	4
147e83
 L(duLcr1):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 	li	rRTN, 1
147e83
 	bgt	cr1, L(dureturn29)
147e83
-	ld	rSHL, -24(r1)
147e83
-	ld	rSHR, -32(r1)
147e83
+	ld	rSHL, rSHLSAVE(r1)
147e83
+	ld	rSHR, rSHRSAVE(r1)
147e83
 	li	rRTN, -1
147e83
 	b	L(dureturn27)
147e83
 	.align	4
147e83
 L(duLcr6):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 	li	rRTN, 1
147e83
 	bgt	cr6, L(dureturn29)
147e83
-	ld	rSHL, -24(r1)
147e83
-	ld	rSHR, -32(r1)
147e83
+	ld	rSHL, rSHLSAVE(r1)
147e83
+	ld	rSHR, rSHRSAVE(r1)
147e83
 	li	rRTN, -1
147e83
 	b	L(dureturn27)
147e83
 	.align	4
147e83
 L(duLcr5):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 	li	rRTN, 1
147e83
 	bgt	cr5, L(dureturn29)
147e83
-	ld	rSHL, -24(r1)
147e83
-	ld	rSHR, -32(r1)
147e83
+	ld	rSHL, rSHLSAVE(r1)
147e83
+	ld	rSHR, rSHRSAVE(r1)
147e83
 	li	rRTN, -1
147e83
 	b	L(dureturn27)
147e83
+
147e83
 	.align	3
147e83
 L(duZeroReturn):
147e83
 	li	rRTN, 0
147e83
 	.align	4
147e83
 L(dureturn):
147e83
-	ld	rWORD8, -8(r1)
147e83
-	ld	rWORD7, -16(r1)
147e83
+	ld	rWORD8, rWORD8SAVE(r1)
147e83
+	ld	rWORD7, rWORD7SAVE(r1)
147e83
 L(dureturn29):
147e83
-	ld	rSHL, -24(r1)
147e83
-	ld	rSHR, -32(r1)
147e83
+	ld	rSHL, rSHLSAVE(r1)
147e83
+	ld	rSHR, rSHRSAVE(r1)
147e83
 L(dureturn27):
147e83
-	ld	rWORD8_SHIFT, -40(r1)
147e83
-L(dureturn26):
147e83
-	ld	rWORD2_SHIFT, -48(r1)
147e83
-L(dureturn25):
147e83
-	ld	rWORD4_SHIFT, -56(r1)
147e83
+	ld	rWORD8_SHIFT, rWORD8SHIFTSAVE(r1)
147e83
+	ld	rWORD2_SHIFT, rWORD2SHIFTSAVE(r1)
147e83
+	ld	rWORD4_SHIFT, rWORD4SHIFTSAVE(r1)
147e83
 L(dureturn24):
147e83
-	ld	rWORD6_SHIFT, -64(r1)
147e83
+	ld	rWORD6_SHIFT, rWORD6SHIFTSAVE(r1)
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	blr
147e83
+
147e83
 L(duzeroLength):
147e83
+	ld	rOFF8,  rOFF8SAVE(r1)
147e83
+	ld	rOFF16, rOFF16SAVE(r1)
147e83
+	ld	rOFF24, rOFF24SAVE(r1)
147e83
+	ld	rOFF32, rOFF32SAVE(r1)
147e83
 	li	rRTN, 0
147e83
 	blr
147e83